About Risco-5
Project Origin
The project began as a summer project aimed at developing a RISC-V core for learning purposes. Initially, a single-cycle version, named Pequeno Risco-5, was developed. The project quickly evolved into a multi-cycle version shortly after its inception.
This project was encouraged by Professor Rodolfo Azevedo from the Institute of Computing at UNICAMP, who suggested the construction of a single-cycle RISC-V processor and later a multi-cycle RISC-V. He also provided the first FPGAs used for testing and assisted with technical questions.
Name
The name Risco-5 is a play on the name RISC-V, the architecture it implements, but it can also suggest something risky.
Risco-5 Family:
- Baby RISCO 5 - RV32E optimized to TinyTapeout: https://github.com/JN513/Baby-Risco-5
- Pequeno RISCO 5 - RV32I single cycle implementation (ARCHIVED): https://github.com/JN513/Pequeno-Risco-5/
- RISCO 5 - RV32I/E[M]: https://github.com/JN513/Risco-5
- Grande RISCO 5 - RV32I Implementation with pipeline: https://github.com/JN513/Grande-Risco-5
- RISCO 5 Bodybuilder - RV64I: Still in speculative phase
- RISCO 5S - RV32IM Simulator writing in C language: https://github.com/JN513/Risco-5S
Developer
Risco-5 was designed by Julio Nunes Avelar and is available for free use under the licenses listed below.
Logo author: Mateus Luck
Licenses
Hardware License: CERN-OHL-P-2.0
Software License: MIT
Documentation License: CC BY-SA 4.0